The present invention generally relates to the preparation of semiconductor material substrates, especially silicon wafers, which are used in the manufacture of electronic components. More particularly, the present invention relates to a single crystal silicon wafer and a method for the preparation thereof. This wafer comprises a surface having an epitaxial silicon layer deposited thereon, and forms an ideal, non-uniform depth distribution of oxygen precipitates during the heat treatment cycles of essentially any electronic device manufacturing process.
Single crystal silicon, which is the starting material for most processes used to fabricate semiconductor electronic components, is commonly prepared by using the Czochralski (xe2x80x9cCzxe2x80x9d) process. Using this method, polycrystalline silicon (xe2x80x9cpolysiliconxe2x80x9d) is charged to a crucible and melted, a seed crystal is brought into contact with the molten silicon, and a single crystal is grown by slow extraction. The first portion of the crystal to be formed during the extraction process is a thin neck. After formation of the neck is complete, the diameter of the crystal is enlarged by decreasing the pulling rate and/or the melt temperature until the desired or target diameter is reached. A cylindrical main body of the crystal which has an approximately constant diameter is then grown by controlling the pull rate and the melt temperature while compensating for the decreasing melt level. Near the end of the growth process, but before the crucible is emptied of molten silicon, the crystal diameter is reduced gradually to form an end-cone. Typically, the end-cone is formed by increasing the crystal pull rate and heat supplied to the crucible. When the diameter becomes small enough, the crystal is then separated from the melt.
A number of defects in single crystal silicon form in the crystal growth chamber as the crystal cools after solidification. Such defects arise, in part, due to the presence of an excess (i.e., a concentration above the solubility limit) of intrinsic point defects, which are known as crystal lattice vacancies and silicon self-interstitials. Silicon crystals grown from a melt are typically grown with an excess of one or the other type of intrinsic point defect. It has been suggested that the type and initial concentration of these point defects in the silicon are determined at the time of solidification and, if these concentrations reach a level of critical supersaturation in the system and the mobility of the point defects is sufficiently high, a reaction (or an agglomeration event) will likely occur. The density of agglomerated intrinsic point defects in Cz silicon is conventionally within the range of about 1xc3x97103/cm3 to about 1xc3x97107/cm3. While these values are relatively low, agglomerated intrinsic point defects are of rapidly increasing importance to device manufacturers and, in fact, are now seen as yield-limiting factors in device fabrication processes and can severely impact the yield potential of the material in the production of complex and highly integrated circuits.
One particularly problematic type of defect is the presence of crystal originated pits (xe2x80x9cCOPsxe2x80x9d). The source of this type of defect is the agglomeration of silicon lattice vacancies. More specifically, when silicon lattice vacancies agglomerate within a silicon ingot, they form voids. Typically, these voids have an octahedral shape and a characteristic size of at least about 0.01 xcexcm. When the ingot is sliced into wafers, these voids are exposed and appear as pits on the surfaces of the wafers. These pits are referred to as COPs.
To date, there generally are three main approaches to dealing with the problem of agglomerated intrinsic point defects. The first approach includes methods which focus on crystal pulling techniques to reduce the number density of agglomerated intrinsic point defects in the ingot. This approach can be further subdivided into those methods having crystal pulling conditions which result in the formation of vacancy dominated material, and those methods having crystal pulling conditions which result in the formation of self-interstitial dominated material. For example, it has been suggested that the number density of agglomerated defects can be reduced by (i) controlling v/G0 (where v is the growth velocity and G0 is the average axial temperature gradient) to grow a crystal in which crystal lattice vacancies are the dominant intrinsic point defect, and (ii) influencing the nucleation rate of the agglomerated defects by altering (generally, by slowing down) the cooling rate of the silicon ingot from about 100xc2x0 C. to about 1050xc2x0 C. during the crystal pulling process. While this approach reduces the number density of agglomerated defects, it does not prevent their formation. As the requirements imposed by device manufacturers become more and more stringent, the presence of these defects will continue to become more of a problem.
Others have suggested reducing the pull rate during the growth of the body of the crystal to a value less than about 0.4 mm/minute. This suggestion, however, is also not satisfactory because such a slow pull rate leads to reduced throughput for each crystal puller. More importantly, such a pull rate leads to the formation of single crystal silicon having a high concentration of self-interstitials. This high concentration, in turn, leads to the formation of agglomerated self-interstitial defects and all the resulting problems associated with such defects.
A second approach to dealing with the problem of agglomerated intrinsic point defects includes methods which focus on the dissolution or annihilation of agglomerated intrinsic point defects subsequent to their formation. Generally, this is achieved by using high temperature heat treatments of the silicon in wafer form. For example, in European Patent Application No. 503,816 A1, Fusegawa et al. propose growing the silicon ingot at a growth rate in excess of 0.8 mm/minute, and heat treating the wafers which are sliced from the ingot at a temperature in the range of 1150xc2x0 C. to 1280xc2x0 C. to reduce the defect density in a thin region near the wafer surface. The specific treatment needed will vary depending on the concentration and location of agglomerated intrinsic point defects in the wafer. Different wafers cut from a crystal which does not have a uniform axial concentration of such defects may require different post-growth processing conditions. Further, such wafer heat treatments are relatively costly, have the potential for introducing metallic impurities into the silicon wafers, and are not universally effective for all types of crystal-related defects.
A third approach to dealing with the problem of agglomerated intrinsic point defects is the epitaxial deposition of a thin crystalline layer of silicon onto the surface of a single crystal silicon wafer. This process provides a single crystal silicon wafer having a surface which is substantially free of agglomerated intrinsic point defects. Use of the traditional epitaxial deposition techniques, however, substantially increases the cost of the wafer.
In addition to containing the above-discussed agglomerated point defects, single crystal silicon prepared by the Cz method also typically contains various impurities, among which is mainly oxygen. This contamination, for example, occurs while the molten silicon is contained in the quartz crucible. At the temperature of the silicon molten mass, oxygen comes into the crystal lattice until it reaches a concentration determined by the solubility of oxygen in silicon at the temperature of the molten mass and by the actual segregation coefficient of oxygen in solidified silicon. Such concentrations are greater than the solubility of oxygen in solid silicon at the temperatures typical for the processes for the fabrication of electronic devices. Thus, as the crystal grows from the molten mass and cools, the solubility of oxygen in it decreases rapidly. This ultimately results in wafers containing oxygen in supersaturated concentrations.
Thermal treatment cycles which are typically employed in the fabrication of electronic devices can cause the precipitation of oxygen in silicon wafers which are supersaturated in oxygen. Depending on their location in the wafer, the precipitates can be harmful or beneficial. Oxygen precipitates located in the active device region of the wafer (i.e., typically near the surface) can impair the operation of the device. Oxygen precipitates located in the bulk of the wafer, however, are capable of trapping undesired metal impurities that may come into contact with the wafer. The use of oxygen precipitates located in the bulk of the wafer to trap metals is commonly referred to as internal or intrinsic gettering (xe2x80x9cIGxe2x80x9d).
Historically, electronic device fabrication processes have included a series of steps which were designed to produce silicon having a region near the surface of the wafer which is free of oxygen precipitates (commonly referred to as a xe2x80x9cdenuded zonexe2x80x9d or a xe2x80x9cprecipitate-free zonexe2x80x9d) with the balance of the wafer (i.e., the wafer bulk) containing a sufficient number of oxygen precipitates for IG purposes. Denuded zones have been formed, for example, in a high-low-high thermal sequence such as (a) oxygen out-diffusion heat treatment at a high temperature ( greater than 1100xc2x0 C.) in an inert gas for a period of at least about 4 hours, (b) oxygen precipitate nuclei formation at a low temperature (600 to 750xc2x0 C.), and (c) growth of oxygen (SiO2) precipitates at a high temperature (1000 to 1150xc2x0 C.). See, e.g., F. Shimura, Semiconductor Silicon Crystal Technology, pp. 361-367 (Academic Press, Inc., San Diego Calif. 1989) (and the references cited therein).
More recently, however, advanced electronic device manufacturing processes, such as DRAM manufacturing processes, have begun to minimize the use of high temperature process steps. Although some of these processes retain enough of the high temperature process steps to produce a denuded zone and sufficient density of bulk precipitates, the tolerances on the material are too tight to render it a commercially viable product. Other current highly advanced electronic device manufacturing processes contain no out-diffusion steps at all. Because of the problems associated with oxygen precipitates in the active device region, therefore, these electronic device fabricators must use silicon wafers which are incapable of forming oxygen precipitates anywhere in the wafer under their process conditions. As a result, IG potential is lost.
In Japanese Patent Application No. 8-24796, Asayama et al. disclose a process for imparting intrinsic gettering into a wafer before it is used in an electronic device manufacturing process. Specifically, Asayama et al. disclose: (a) baking silicon wafers at 1150xc2x0 C. in a H2 atmosphere; (b)depositing epitaxial layers onto the surfaces of the wafers at temperatures of 1100, 1150, and 1200xc2x0 C.; and (c) cooling the wafers at rates of 5, 10, and 15xc2x0 C./sec. The wafers analyzed by Asayama et al. had a resistivity of no greater than 0.5 xcexa9cm and an oxygen density of 11xc3x971017 atoms/cm3 (in other words, about 22 ppm (i.e., 22 oxygen atoms per 1,000,000 total atoms in the wafer)). Asayama et al. conclude that if the process is used with a temperature of from 1150 to 1250xc2x0 C. and a cooling rate of 10 to 100xc2x0 C./sec, such wafers will form a desirable oxygen precipitate profile upon being heated over a period of time at a temperature of from 700 to 1000xc2x0 C.
Among the objects of the present invention is the provision of a single crystal silicon wafer which (a) has an epitaxial surface that is essentially free of crystal originated pits; and (b) forms an ideal, non-uniform depth distribution of oxygen precipitates during a heat treatment cycle of essentially any electronic device manufacturing process.
Briefly, therefore, this invention is directed to a single crystal silicon wafer comprising: (a) two major generally parallel surfaces (i.e., the front and back surfaces); (b) a central plane between and parallel to the front and back surfaces; (c) a front surface layer which comprises the region of the wafer extending a distance, D1, of at least about 10 xcexcm from the front surface toward the central plane; and (d) a bulk layer which comprises the region of the wafer extending from the central plane to the front surface layer. This wafer is characterized in that the wafer has a non-uniform distribution of crystal lattice vacancies wherein (a) the concentration of crystal lattice vacancies in the bulk layer is greater than the concentration of crystal lattice vacancies in the front surface layer, (b) the crystal lattice vacancies have a concentration profile having a peak density of crystal lattice vacancies at or near the central plane, and (c) the concentration of crystal lattice vacancies generally decreases from the position of peak density toward the front surface of the wafer. In addition, the front surface of the wafer has an epitaxial layer deposited thereon. This epitaxial layer has a thickness of from about 0.1 to about 2.0 xcexcm.
In another embodiment directed to a single crystal silicon wafer, the wafer comprises: (a) two major generally parallel surfaces (i.e., a front surface and a back surface); (b) a central plane between and parallel to the front and back surfaces; (c) a front surface layer which comprises the region of the wafer extending a distance, D2, of at least about 10 xcexcm from the front surface toward the central plane; and (d) a bulk layer which comprises the region of the wafer extending from the central plane to the front surface layer. In this embodiment, the wafer has a non-uniform distribution of crystal lattice vacancies wherein (a) the concentration of crystal lattice vacancies in the bulk layer is greater than the concentration of crystal lattice vacancies in the front surface layer, (b) the crystal lattice vacancies have a concentration profile having a peak density of crystal lattice vacancies at or near the central plane, and (c) the concentration of crystal lattice vacancies generally decreases from the position of peak density toward the front surface of the wafer. In addition, the front surface of the wafer has an epitaxial layer deposited thereon. This epitaxial layer comprises a surface having an average light scattering event concentration of no greater than about 0.06/cm2, as measured by a laser-based auto inspection tool configured to detect light scattering events corresponding to polystyrene spheres having diameters of no less than about 0.12 xcexcm. Also in this embodiment, the bulk layer comprises voids which are at least about 0.01 xcexcm in their largest dimension.
In an additional embodiment directed to a single crystal silicon wafer, the wafer comprises: (a) two major generally parallel surfaces (i.e., the front and back surfaces), (b) a central plane between and parallel to the front and back surfaces, (c) a front surface layer comprising the region of the wafer extending a distance of no more than about 100 xcexcm from the front surface toward the central plane, and (d) a bulk layer comprising the region of the wafer extending from the central plane to the front surface layer. In this embodiment, the bulk layer has a substantially uniform oxygen concentration and a concentration of crystal lattice vacancies such that upon subjecting the wafer to an oxygen precipitation heat treatment consisting essentially of annealing the wafer at 800xc2x0 C. for about 4 hours and then at 1000xc2x0 C. for 16 hours, the wafer will contain oxygen precipitates having a concentration profile in which the peak density of the precipitates in the bulk layer is at or near the central plane with the concentration of the precipitates in the bulk layer generally decreasing in the direction of the front surface layer. In addition, the front surface of the wafer has an epitaxial layer deposited thereon. This epitaxial layer has a thickness of from about 0.1 to about 2.0 xcexcm.
In a further embodiment directed to a single crystal silicon wafer, the wafer comprises: (a) two major generally parallel surfaces (i.e., a front surface and a back surface), (b) a central plane between and parallel to the front and back surfaces, (c) a front surface layer comprising the region of the wafer extending a distance of no more than about 100 xcexcm from the front surface toward the central plane, and (d) a bulk layer comprising the region of the wafer extending from the central plane to the front surface layer. In this embodiment, the bulk layer has a substantially uniform oxygen concentration and a concentration of crystal lattice vacancies such that upon subjecting the wafer to an oxygen precipitation heat treatment consisting essentially of annealing the wafer at 800xc2x0 C. for about 4 hours and then at 1000xc2x0 C. for 16 hours, the wafer will contain oxygen precipitates having a concentration profile in which the peak density of the precipitates in the bulk layer is at or near the central plane with the concentration of the precipitates in the bulk layer generally decreasing toward the front surface layer. The bulk layer also comprises voids which are at least about 0.01 xcexcm in their largest dimension. The front surface of the wafer has an epitaxial layer deposited thereon. This epitaxial layer comprises a surface having an average light scattering event concentration of no greater than about 0.06/cm2, as measured by a laser-based auto inspection tool configured to detect light scattering events corresponding to polystyrene spheres having diameters of no less than about 0.12 xcexcm.
This invention is also directed to a process for the preparation of a silicon wafer comprising a surface having an epitaxial layer deposited thereon. In one embodiment, the process comprises first heating a surface of a wafer starting material in an oxidant-free atmosphere to remove a silicon oxide layer from the surface. Within about 30 seconds after removing the silicon oxide layer from the surface, the surface is exposed to an atmosphere comprising silicon to deposit a silicon epitaxial layer onto the surface to form an epitaxial wafer. The epitaxial wafer is then heated to a soak temperature of at least about 1175xc2x0 C. while exposing the epitaxial layer to an oxidizing atmosphere comprising an oxidant. Afterwards, the heated epitaxial wafer is cooled at a rate of at least about 10xc2x0 C./sec.
In another embodiment directed to a process for the preparation of a silicon wafer comprising a surface having an epitaxial layer deposited thereon, the process comprises first heating a surface of a wafer starting material to a temperature of at least about 1100xc2x0 C. in an oxidant-free atmosphere to remove a silicon oxide layer from the surface. Within about 30 seconds after the surface reaches 1100xc2x0 C., the surface is exposed to an atmosphere comprising silicon to deposit a silicon epitaxial layer onto the surface to form an epitaxial wafer. The epitaxial wafer is then heated to a soak temperature of at least about 1175xc2x0 C. while exposing the epitaxial layer to an oxidizing atmosphere comprising an oxidant. Afterwards, the heated epitaxial wafer is cooled at a rate of at least about 10xc2x0 C./sec.
In another embodiment directed to a process for the preparation of a silicon wafer comprising a surface having an epitaxial layer deposited thereon, the process comprises first heating a surface of a wafer starting material to a temperature of at least about 1150xc2x0 C. in an oxidant-free atmosphere to remove a silicon oxide layer from the surface. Within about 30 seconds after the surface reaches 1150xc2x0 C., the surface is exposed to an atmosphere comprising silicon to deposit a silicon epitaxial layer onto the surface to form an epitaxial wafer. The epitaxial wafer is then heated to a soak temperature of at least about 1175xc2x0 C. while exposing the epitaxial layer to an oxidizing atmosphere comprising an oxidant. Afterwards, the heated epitaxial wafer is cooled at a rate of at least about 10xc2x0 C./sec.
In an additional embodiment directed to a process for the preparation of a silicon wafer comprising a surface having an epitaxial layer deposited thereon, the process comprises first depositing an epitaxial layer onto a surface of a wafer to form an epitaxial wafer. The epitaxial wafer is then heated to a soak temperature of at least about 1175xc2x0 C. while exposing the epitaxial layer to an oxidizing atmosphere comprising an oxidant. Afterwards, the heated epitaxial wafer is cooled at a rate of at least about 10xc2x0 C./sec. In this embodiment, the epitaxial layer is not contacted with a post-epitaxial-deposition cleaning solution before the epitaxial wafer is heated to the soak temperature.
In a further embodiment directed to a process for the preparation of a silicon wafer comprising a surface having an epitaxial layer deposited thereon, the process comprises first heating a wafer comprising a surface with an epitaxial layer deposited thereon to a soak temperature of at least about 1175xc2x0 C. while exposing the epitaxial layer to an oxidizing atmosphere comprising an oxidant. The heated wafer is then cooled at a rate of at least about 10xc2x0 C./sec. In this embodiment, the epitaxial layer has a thickness of at least about 0.1 xcexcm and less than 2.0 xcexcm.
In another embodiment directed to a process for the preparation of a silicon wafer comprising a surface having an epitaxial layer deposited thereon, the process comprises first depositing an epitaxial layer onto a surface of a wafer starting material to form an epitaxial wafer. The epitaxial wafer is heated to a soak temperature of at least about 1175xc2x0 C. while exposing the epitaxial layer to an oxidizing atmosphere comprising an oxidant. Afterwards, the heated epitaxial wafer is cooled at a rate of at least about 10xc2x0 C./sec. In this embodiment, the surface of the wafer starting material (before the epitaxial layer is deposited onto the surface) has an average light scattering event concentration of at least about 0.5/cm2 as measured by a laser-based auto inspection tool configured to detect light scattering events corresponding to polystyrene spheres having diameters of no less than about 0.12 xcexcm.
In yet another embodiment directed to a process for the preparation of a silicon wafer comprising a surface having an epitaxial layer deposited thereon, the process comprises first heating a surface of a wafer starting material to a temperature of at least about 1150xc2x0 C. in an atmosphere consisting essentially of H2 to remove a silicon oxide layer from the surface. Within about 10 seconds after the surface reaches 1150xc2x0 C. the surface is exposed to an atmosphere comprising SiHCl3 to deposit a silicon epitaxial layer onto the surface to form an epitaxial wafer. The epitaxial wafer is then heated to a soak temperature of at least about 1175xc2x0 C. while exposing the epitaxial layer to an oxidizing atmosphere comprising O2. Afterwards, the epitaxial wafer is cooled at a rate of at least about 20xc2x0 C./sec from the soak temperature to about 250xc2x0 C. below the soak temperature. In this embodiment, the epitaxial layer has a thickness of from about 0.65 to 1.0 xcexcm, and the concentration of the O2 in the oxidizing atmosphere is from about 300 to about 500 ppm.
This invention is also directed to a process for heating and rapidly cooling a single crystal silicon wafer in a reactor constructed for depositing a silicon epitaxial layer onto a surface of a wafer. This process comprises heating the wafer to a soak temperature of at least about 1175xc2x0 C., and cooling the heated wafer at a rate of at least about 10xc2x0 C./sec. In this embodiment, the wafer is supported on a susceptor during the heating step and is removed from contact with the susceptor during the cooling step.
Other features of this invention will be in part apparent and in part pointed out hereinafter.